This invention generally relates to electronic systems and in particular it relates to a configurable voltage translating buffer.
A dual power supply system involves two sets of logic levels. Signal levels to the control inputs of a translating buffer can be incompatible with the buffer threshold, resulting in high power dissipation and/or nonfunctionality.
In a traditional prior art voltage translating buffer, one data port""s inputs are referenced to the first power supply voltage VccA and the other port""s inputs are referenced to the second power supply voltage VccB. The supply voltage that the control inputs are referenced to is an arbitrary hardwired choice made by the chip designer. Some prior art devices are offered in two versions, one with the control input referenced to VccA, and the other referenced to VccB. The end user has to make sure that the control signal logic levels are compatible with that arbitrarily chosen reference.
If the user applies voltage swings whose input high voltage Vih is higher than the reference, then there is no problem, assuming the inputs are overvoltage tolerant. However, since the input threshold is set lower than the midpoint of the incoming signal, the applied signal should swing rail to rail to maximize noise margins.
But if the user applies signal swings whose Vih is lower than the reference, then the input buffer is in a high static current mode because it is not biased fully off. This state is commonly known as the delta-Icc condition. This can cause high power dissipation, especially in situations where the control inputs are biased high most of the time.
A voltage configurable circuit includes: a first transistor having a first end coupled to a first power supply node; a second transistor having a first end coupled to a second power supply node and cross-coupled with the first transistor; input buffers having input buffer supply nodes coupled to a second end of the first transistor and a second end of the second transistor; a first output port coupled to a first one of the input buffers; and a second output port coupled to a second one of the input buffers.